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AMD 7nm Epyc CPU offers core enhancements, high performance gains



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On its next Horizon event today, AMD revealed significant new details about its 7nm server CPU, the code name of Rome. The new chip debut in significant time for AMD. The first server CPU, Epyc, has won accolades and adoption, including a new announcement from Amazon. Epyc 2 is even more important in some ways. Businesses are inherently conservative and companies do not tend to jump from CPU provider to CPU provider by drop off a hat. Pushing AMD processors into multiple businesses means demonstrating a sustained road map and ability to deliver new product generations that continue to compete effectively. AMD's room information means that their first 7nm chip will actually deliver on these gains. (Excuse me for potato photos – I'm a reputable miserable photographer.)

According to AMD's CTO, Mark Papermaster, second generation Epyc processors will contain a number of significant improvements over the original design. Floating point throughput has doubled thanks to the adoption of 256-bit AVX2 registries. Load / Large bandwidth is also doubled, and the CPU's shipping and retirement bandwidth has both increased and it has the micro-up cache. Epyc

These improvements should overall increase Epyc and Ryzen performance significantly, although AMD did not indicate if it would reduce the clock frequency of 7nm Ryzen and Epyc CPUs when running AVX2 just as Intel does. 128-bit AVX2 support worked quite well for AMD in Ryzen server tests and comparisons showed that while Intel had some advantage in some FPU workloads, AMD was quite strong, or even performance-leading with others.

As for PCIe 4.0 support, AMD will provide backward compatibility with existing Naples platforms and future compatibility with AMD's Milan platform, guaranteed. This means that the CPU can use either PCIe 3.0 or 4.0 depending on the current platform.

Infinity Fabric also gets a big update, but some details were not revealed. As someone has predicted, Epyc 2 will be AMD's first CPU to distribute tepler based on 7nm while the I / O block is built at 14nm. This is not necessarily a bad thing. As the pitch shrinks has evolved, the contact and coupling resistance have become a major limiting factor for improving overall performance. It is not necessarily much advantage to simply pack more wires and pads into smaller and smaller spaces – and then AMD shares its I / O and tricks into two separate sections.

AMD's current Infinity Fabric implementation is linked as below focusing on lighter arrows in each CPU, not cross-CPU links.)

The new second generation Infinity Fabric looks quite different: [19659004]

It is not clear what impact this will have on the waiting time, but it shows how AMD will avoid what could be a significant problem. With eight DDR4 channels and probably doubled chip density (AMD referred to this without giving any formal kernel count for Epyc 2), AMD would have had only one DDR4 channel per eight CPU kernels. It is significantly lower than the previous design. This approach should avoid this problem by providing full DDR4 bandwidth available for whatever kernels need to access it.

There are still a number of specific details we do not have, including information about how much Infinity Fabric power has improved or how much bandwidth it provides in the new CPUs. I would warn readers to conclude that these load / storage and CPU throughput improvements will have a major impact on performance. The level of uplifting will depend on applications and where the bottlenecks were in the original Epyc design. Haswell, if you remember, promised a number of significant low bandwidth and throughput gains, but the actual uplifted in most software was far less.

Still, Epyc 2 looks like a strong chip based on what we've seen so far. We do not know exact clocks or kernel distribution, in addition to a maximum 64-core CPU (a comment from the scene seemed to mean that the clock scale of 7nm is small, but we have not been able to confirm it yet). However, between the IPC gains and the expected core number increases, Epyc 2 should deliver significant gains compared to its predecessor.

According to Lisa Su, Roma will offer a 2x performance per socket and a 4x improvement in FPU performance per shelf based on previous generation CPUs. It's a major claimed improvement and we expect it to reflect best case scenarios – obviously, applications that do not scale perfectly from 32 kernels to 64 kernels will not hit the target – but under the right circumstances, Epyc 2 should be a performance titanium.

One claims this? AMD gave absolutely no guidance as to when the CPU can start, beyond "2019." No 1H, no 2H. This latest information, delivered in the tail end of the presentation, makes it much more difficult to judge the potential of the launch. If 1H is usually read to mean "June", "2019," can be read to mean "December" under exactly the same theory. It seems unlikely that this would be true, but the lack of a quarterly timeframe sapped the energy of AMD's announcement in general.

Now Read : Nvidia Tesla, AMD Epyc to Power New Berkeley Supercomputer, Epyc Achievement: AMD now available for Oracle Cloud Compute Instances, and AMD Will Fab's 7nm Rome, # 39; Epyc CPUs on TSMC, not GlobalFoundries


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