7nm, 7+, 7 ++, with Next Gen Packaging

At Intel's Investor Day today, CEO Bob Swan and Murthy Renduchintala spoke to the company's capability in terms of production capacity. Intel has historically been strong in its ability to exercise its process technology, but the delay of the 10nm process has obviously raised several question marks and has been doing for several years. The two Intel leaders went into a little detail on what Intel did in the meantime and how it learned from the issues.

Back in 2013, Intel anticipates its 10nm to succeed 14nm by providing 2.7x density, with new technologies such as Self-Aligned Quad Patterning (SAQP), Active Gate Contact (COAG), Cobolt Connections and New Packaging Technologies like EMIB and Foveros. Intel admits that this was an ambitious plan, and the goals were not clearly defined by the teams, and it was ultimately too complicated and not ideally done.

This ended up pushing 10nm out in a later time frame. In this case Intel pushed 10nm out until 2019 (technically they sent Cannon Lake in small quantities 10nm in 2017, but there is nothing more than a curiosity in the timeline of the semiconductors) and filled the gap with 14+ and 14 ++.

Intel's 14+ and 14++ processes gained more than 20% more performance (from Broadwell to Whiskey Lake) from the process since its inception. As a result, Intel is prepared to not only get ready for future intra-node optimizations, but actually adapt the road map to compensate for it. Murthy made it clear that Intel will introduce a Moore's law-like win at the beginning of a new process and another similar gain at the end of the process.

Intel has stated that its 10nm product family (beyond Cannon Lake) will begin to be available from the middle of this year (2019), with Ice Lake on client platforms (notebooks).

Intel will launch more 10nm products through 2019 and 2020, including server-based 10nm in the first half of 2020:

In the above slide, Intel says it will have 7nm in production and launch of a product in 2021. It sounds very aggressive to a company that has had problems with 10nm. It even shows in Intel's root directory, with 10nm (and 10 + and 10 ++) that has a much shorter life cycle than the 14nm family of processes.

With this in mind, Intel's 7nm comes to be the combination of what Intel has learned from the product category 14nm and 10nm. Intel wants the 2x scaling (Moores Law), but with intra-node optimizations planned as part of the roadmap. Intel also reduces the number of design rules, which should contribute to execution. 7nm will also be where Intel crosses with EUV and also introduce next-generation Foveros and EMIB packing.

Intel provided this slide, which shows a monolithic PC-Centric door with a multi-die data center chip built on both Foveros and EMIB. This confirms our discussion with Intel's chipset and packing team, who also stated that we would see Foveros and EMIB on a combined product – especially the GPU.

Intel announced that its leading 7nm product (lead = top, or lead = first?) Would be the new GPGPU, built on the Xe graphics architecture. Intel has stated that its Xe product stack will have two different micro-architectures from mobile client up to GPGPU, with one of the architectures called Arctic Sound. Technically, Intel will launch its first discrete GPU in 2020 according to the press release, but 7nm GPGPU will be launched in 2021.

More information comes out of Intel's event, more to follow.

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Source: Intel

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